Booth multiplier is the key component in portable very large-scale integration (VSLI) systems enabled with signal and image processing applications. The area, delay, and energy are the major constraints in these systems. Therefore, in this paper, a detailed analysis of the state-of-the-art Booth multiplier architecture and its various internal units are presented to find the scope of optimization. Based on the finding of analysis, optimized new binary to 2's complement (B2C), Booth encoder-cum-selector type-1 and type-2, and partial product addition units are proposed. Furthermore, using these optimized units, an efficient parallel radix-4 8×8 Booth multiplier architecture is proposed. The simulation is carried out to verify the functionality of the proposed design. The synthesis results show that the proposed structure offers a saving of 13.56% in delay and 34.87% in area compared to the recent similar Booth multiplier design. Comparison results also reveal that the proposed Booth multiplier design involves 43.7% less area-delay-product and 11.24% less energy compared to the recent Booth multiplier design. Therefore, the proposed Booth multiplier design could be helpful for efficient realization of digital signal processing systems.
Area, Booth encoding, delay, energy, multiplier, VLSI
SINGHAL, SUBODH; PATEL, SUJIT; MAHAJAN, ANURAG; and SAXENA, GAURAV
"Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications,"
Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 29:
4, Article 10.
Available at: https://journals.tubitak.gov.tr/elektrik/vol29/iss4/10