Turkish Journal of Electrical Engineering and Computer Sciences






Electrical transport across the poly/monocrystalline silicon (poly-Si/c-Si) interface has been investigated by introducing variations in the interface treatment process affecting the thickness of the native oxide layer formed on the silicon surface. The I-V relationship characterizing the resistance associated with this interface is extracted using an improved open-collector method, which eliminates the inherent nonlinearity arising from the reverse active characteristics of the bipolar transistor. The nonohmic behavior of the interface at low electric fields is demonstrated to be consistent with direct tunneling through a rectangular barrier presented by an ultrathin interfacial oxide layer. An approximate tunnel junction model is proposed that fits the tunneling current in the low bias regime, predicting the experimentally observed increase in the low-voltage leakage current associated with ultrathin oxides. The thickness of the interfacial oxide extracted by fitting the measured data to the proposed rectangular-barrier tunnel junction model is in good agreement with reported experimental values. Finally, a relation between experimentally introduced variations in the interface treatment process and the magnitude of the resistance associated with the interface is identified, which can be quantitatively explained based on the direct tunnel junction model in terms of differences in the native oxide thickness.


Heterojunction bipolar transistor, polysilicon emitter, semiconductor-insulator interfaces, series emitter resistance, tunneling

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