Turkish Journal of Electrical Engineering and Computer Sciences




Billions of smart objects in the edge devices offer advanced connectivity to networks which increase the security and complexity of the Internet of things (IoT) applications. To make such entities smarter heterogeneous intellectual property (IP) cores from multiple service providers are reused in system on chip platform. Enabling both chip and IP protection at post fabrication level is imperative. The IoT-based IP cores are signed with the hybrid physical unclonable function and finite state machine model to protect from cloning, misuse, unauthorized user access, and physical attacks. The extended finite-state machine is used to verify the signature, which reduces the space and time complexity. The goal is to design a secure plug-and-play system which supports IoT IP core for the unique chip without using any complex algorithms and huge memory storage. Experimental results show that the average overhead values of area and power are 1.05 % and 1.08 % less, respectively, compared with the existing IP protection.


System on chip field-programmable gate arrays, heterogeneous intellectual property cores, physical unclonable function, finite state machine, intellectual property protection

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