Turkish Journal of Electrical Engineering and Computer Sciences




Floating point arithmetic circuits provide wide dynamic range and high precision, and they are widely used in scientific computing and signal processing applications, but the complexity increases in hardware implementations of floating point units. In VLSI design architecture, many applications suffer in size of the components used in logical operations. The aim of reducing architecture is to gain reduction in power loss and also in area, but the reduction in size of the components leads to an increase in delay and memory. Hence, to overcome these limitations and to optimize the area, a novel design of floating point processing element (FPPE) architecture is proposed in this work with a smaller number of logical components and registers. A partially folded arithmetic function architecture is modeled for the design of an infinite impulse response (IIR) filter using FPPE and implemented on a field programmable gate array (FPGA) with efficient area. FPGAs are widely used in the implementation of floating point computing modules due to the increase in gate density and embedded arithmetic cores. Synthesis results prove that the proposed design of the IIR filter provides efficient area compared with existing works. The modules are designed in Verilog and implemented on Xilinx FPGAs.


Field programmable gate arrays, floating point arithmetic, floating point processing element, IEEE 754-2008 standard, infinite impulse response filters

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