Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consumes larger power. Traditional NOR and NAND match-line (ML) architectures suffer from a short circuit current path sharing and charge sharing respectively during precharge. The recently proposed precharge-free CAM suffers from high search delay and the subsequently proposed self-controlled precharge-free CAM suffers from high power consumption. This paper presents a hybrid self-controlled precharge-free (HSCPF) CAM architecture, which uses a novel charge control circuitry to reduce search delay as well as power consumption. The proposed and existing CAM ML architectures were developed using CMOS 45nm technology node with a supply voltage of 1 V. Simulation results show that the proposed HSCPF CAM-type ML design reduces power consumption and search delay effectively when compared to recent precharge-free CAM-type ML architectural designs.
Content-addressable memory, low power, match-line, precharge-free, search delay
SATTI, V V SATYANARAYANA and SRIADIBHATLA, SRIDEVI
"Hybrid self-controlled precharge-free CAM design for low power and high performance,"
Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 27:
2, Article 34.
Available at: https://journals.tubitak.gov.tr/elektrik/vol27/iss2/34