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Turkish Journal of Electrical Engineering and Computer Sciences

DOI

10.3906/elk-1707-352

Abstract

This paper presents a low quiescent current, fast settling time, and adaptively biased capacitor less low-dropout (LDO) regulator. The topology involves a segmented pass transistor with bulk modulation and adaptively biased current control stages to improve the transient performance. The bulk modulation of the pass transistor assists in fast settling of the output voltage. The frequency compensation makes the LDO voltage regulator stable adaptively over load current transitions. In addition, the biasing stage is designed such that it adapts to the load transitions while consuming the quiescent current abstemiously. This arrangement further improves settling time to be within 1 µs while restricting undershoot/overshoot to 171 mV/82 mV for a load current transition between 0 and 100 mA with load capacitor of 40 pF. The LDO regulator is designed using 0.18 $\mu$m UMC CMOS process by consuming 1.5 $\mu$A quiescent current at no loads.

First Page

2385

Last Page

2394

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