A data-aware write-assist 10T SRAM cell with bit-interleaving capability

Authors

SHIVRAM MANSORE
RADHESHYAM GAMAD

DOI

10.3906/elk-1801-272

Abstract

Cell stability is becoming an important design concern as process technology continues to scale down. In this paper, we present a single-ended 10T SRAM cell that improves simultaneously both read static noise margin (RSNM) and write static noise margin (WSNM) by employing separate read buffer and power gating transistors, respectively. The cross-point write structure of the proposed cell facilitates bit-interleaved architecture to enhance soft-error immunity. Simulation is done on $65$-nm CMOS technology on Cadence. Simulation results show that the RSNM of the proposed SRAM cell is 2.78 times and 1.47 times higher than those of the conventional 6T and Schmitt trigger-based 10T (ST-2) cells, respectively, at $0.4$ V. The WSNM of the proposed design is 5.14 times larger than that of the two-port disturb-free 9T (TPDF9T) cell (without write assist) at $0.4$ V. Write delay of the proposed cell is 77.56 % less than that of the TPDF9T cell at $0.4$ V. Leakage power dissipation of the proposed SRAM cell is 0.89 times that of the ST-2 cell at $0.4$ V. The proposed cell occupies 1.34 times more area than the conventional 6T cell.

Keywords

Bit interleaving, leakage power, SRAM, write ability

First Page

2361

Last Page

2373

Recommended Citation

MANSORE, SHIVRAM and GAMAD, RADHESHYAM (2018) "A data-aware write-assist 10T SRAM cell with bit-interleaving capability," Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 26: No. 5, Article 16. https://doi.org/10.3906/elk-1801-272
Available at: https://journals.tubitak.gov.tr/elektrik/vol26/iss5/16