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Turkish Journal of Electrical Engineering and Computer Sciences

DOI

10.3906/elk-1711-220

Abstract

A through-silicon via (TSV) is established as the main enabler for a three-dimensional integrated circuit (3D IC) that increases system density and compactness. The exponential increase in TSV density led to TSV-induced catastrophic and parametric faults. We propose an original architecture that detects errors caused by TSV manufacturing defects. The proposed design for testability is a built-in technique that detects errors in an early manufacturing stage and is hence very economically attractive. The proposal is capable of testing each and every TSV in the network. The technique achieves high fault coverage and high observability.

First Page

1909

Last Page

1921

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