A novel efficient TSV built-in test for stacked 3D ICs

Authors

BADI GUIBANE
BELGACEM HAMDI
BRAHIM BEN SALEM
ABDELLATIF MTIBAA

DOI

10.3906/elk-1711-220

Abstract

A through-silicon via (TSV) is established as the main enabler for a three-dimensional integrated circuit (3D IC) that increases system density and compactness. The exponential increase in TSV density led to TSV-induced catastrophic and parametric faults. We propose an original architecture that detects errors caused by TSV manufacturing defects. The proposed design for testability is a built-in technique that detects errors in an early manufacturing stage and is hence very economically attractive. The proposal is capable of testing each and every TSV in the network. The technique achieves high fault coverage and high observability.

Keywords

3D IC, through-silicon via, built-in current sensor, built-in self-test, design for testability, test access mechanism

First Page

1909

Last Page

1921

Recommended Citation

GUIBANE, BADI; HAMDI, BELGACEM; SALEM, BRAHIM BEN; and MTIBAA, ABDELLATIF (2018) "A novel efficient TSV built-in test for stacked 3D ICs," Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 26: No. 4, Article 19. https://doi.org/10.3906/elk-1711-220
Available at: https://journals.tubitak.gov.tr/elektrik/vol26/iss4/19