•  
  •  
 

Turkish Journal of Electrical Engineering and Computer Sciences

DOI

10.3906/elk-1708-179

Abstract

This paper presents a new realization for a CMOS four-quadrant analogue multiplier. The proposed circuit is composed of three second generation current conveyor circuits (CCII), two NMOS transistors operating in the linear region, and four passive resistances. It can be operated in current mode and voltage mode without changing the circuit topology. The simulations results of the proposed mixed mode multiplier are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 $\mu $m CMOS process available from MOSIS at 25 $^{\circ}$C with $\pm $0.8 V supply voltage. Through the use of resistive compensation with different passive resistance values, the voltage mode responses present $\pm $0.25 V dynamic range with THD less than 0.114% and wide bandwidth extended from 3.42 GHz to 4.1 GHz. The current mode responses show $\pm $150 $\mu $A dynamic range with a maximum THD value about 0.083% and large bandwidth expanded from 2.67 GHz to 3.12 GHz.

First Page

882

Last Page

894

Share

COinS