This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput. However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: $\pi $/2) of the sine wave. The ROM is partitioned into three four-bit sub-ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24-bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub-ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15% and 14.8%, respectively.
Phase accumulator, carry look-ahead adder, direct digital frequency synthesizer, read-only memory
ALKURWY, SALAH; ALI, SAWAL; ISLAM, MD.SHABIUL; and IDROS, MD. FAIZUL
"A low power memoryless ROM design architecture for a direct digital frequency synthesizer,"
Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 25:
5, Article 43.
Available at: https://journals.tubitak.gov.tr/elektrik/vol25/iss5/43