Turkish Journal of Electrical Engineering and Computer Sciences
DOI
10.3906/elk-1601-185
Abstract
This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of $\sqrt {2N} $ improvement in TDC resolution with $N$ parallel TDC channels. Suppressed noise in the TDC allows the ADPLL to achieve superior jitter performance in both theoretical calculations and simulation results. In order to allow fast portability between process nodes, short design cycle time, ease of modification, and flexibility, ADPLL architecture is designed completely in register transfer level intensive Verilog code and the implementation is synthesized in order to obtain final microelectronic design schematics. In comparison to similar work in the literature, postlayout simulation results show that the designed ADPLL achieves period jitter of 1.78 ps$_{rms}$ with a layout area of 0.09 mm$^{2}$ in 65 nm CMOS process and power consumption of 17.5 mW at 800 MHz.
Keywords
All-digital phase-locked loop, time-to-digital converter, digitally controlled oscillator, quantization noise suppression
First Page
2410
Last Page
2423
Recommended Citation
BALCIOĞLU, YALÇIN and DÜNDAR, GÜNHAN
(2017)
"A 0.65-1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter,"
Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 25:
No.
3, Article 63.
https://doi.org/10.3906/elk-1601-185
Available at:
https://journals.tubitak.gov.tr/elektrik/vol25/iss3/63
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Computer Engineering Commons, Computer Sciences Commons, Electrical and Computer Engineering Commons