Turkish Journal of Electrical Engineering and Computer Sciences
Abstract
In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications. The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A test chip of the 0.042 mm$^{2}$ DLL and the 3-ps-adjustable-resolution phase shifters with a 0.0025 mm$^{2}$ per-channel area was implemented using a 90-nm CMOS process. Simulation results show that the phase error of the 90$^{\circ}$ phase shifter at 1.6 GHz is 2.4$^{\circ}$. The DLL and the phase shifter consume 3.4 mW and 0.31 mW, respectively, at 1.6 GHz.
DOI
10.3906/elk-1606-38
Keywords
Digital delay-locked loops, phase detection, phase shifters, delay lines
First Page
2185
Last Page
2194
Recommended Citation
CHUNG, C, & YU, C (2017). An area-efficient and wide-range digital DLL for per-pin deskew applications. Turkish Journal of Electrical Engineering and Computer Sciences 25 (3): 2185-2194. https://doi.org/10.3906/elk-1606-38
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