In this work, a 3-bit feedforward 3rd order sigma delta analog-to-digital converter (ADC) is presented. In this proposed architecture, feedforward paths and multibit design help the integrator output swings to become smaller, which renders the exploitation of a telescopic cascode opamp in the integrators possible. Moreover, a double sampling method is used to relax the opamp specifications. The proposed sigma delta ADC consumes 28.2 $\mu $W and has 81.3 dB SNDR according to postlayout simulations.
Sigma delta, analog-to-digital converter, feedforward, 3rd order
AKÇAKAYA, FEYYAZ MELİH and DÜNDAR, GÜNHAN
"Low power 3rd order feedforward sigma delta ADC design,"
Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 25:
1, Article 12.
Available at: https://journals.tubitak.gov.tr/elektrik/vol25/iss1/12