Low power 3rd order feedforward sigma delta ADC design

Authors

FEYYAZ MELİH AKÇAKAYA
GÜNHAN DÜNDAR

DOI

10.3906/elk-1507-204

Abstract

In this work, a 3-bit feedforward 3rd order sigma delta analog-to-digital converter (ADC) is presented. In this proposed architecture, feedforward paths and multibit design help the integrator output swings to become smaller, which renders the exploitation of a telescopic cascode opamp in the integrators possible. Moreover, a double sampling method is used to relax the opamp specifications. The proposed sigma delta ADC consumes 28.2 $\mu $W and has 81.3 dB SNDR according to postlayout simulations.

Keywords

Sigma delta, analog-to-digital converter, feedforward, 3rd order

First Page

155

Last Page

162

Recommended Citation

AKÇAKAYA, FEYYAZ MELİH and DÜNDAR, GÜNHAN (2017) "Low power 3rd order feedforward sigma delta ADC design," Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 25: No. 1, Article 12. https://doi.org/10.3906/elk-1507-204
Available at: https://journals.tubitak.gov.tr/elektrik/vol25/iss1/12