Turkish Journal of Electrical Engineering and Computer Sciences
Abstract
In this work, a 3-bit feedforward 3rd order sigma delta analog-to-digital converter (ADC) is presented. In this proposed architecture, feedforward paths and multibit design help the integrator output swings to become smaller, which renders the exploitation of a telescopic cascode opamp in the integrators possible. Moreover, a double sampling method is used to relax the opamp specifications. The proposed sigma delta ADC consumes 28.2 $\mu $W and has 81.3 dB SNDR according to postlayout simulations.
DOI
10.3906/elk-1507-204
Keywords
Sigma delta, analog-to-digital converter, feedforward, 3rd order
First Page
155
Last Page
162
Recommended Citation
AKÇAKAYA, F. M, & DÜNDAR, G (2017). Low power 3rd order feedforward sigma delta ADC design. Turkish Journal of Electrical Engineering and Computer Sciences 25 (1): 155-162. https://doi.org/10.3906/elk-1507-204
Included in
Computer Engineering Commons, Computer Sciences Commons, Electrical and Computer Engineering Commons
