FPGA implementation of a HEVC deblocking filter for fast processing of super high resolution applications

Authors

AWAIS KHAN
GULISTAN RAJA

DOI

10.3906/elk-1407-144

Abstract

This paper proposes the architecture of a deblocking filter (DBF) that removes blocking artifacts in new emerging High Efficiency Video Coding (HEVC). A parallel architecture for both normal and strong filtering modes of HEVC is proposed. Distributed memories and two data paths increase the parallelism and make the architecture more efficient. The proposed architecture is described by Verilog and implemented on FPGA. The architecture can realize real time to compute 4K UHD video at 30 fps by using 46.65 million clocks with total equivalent gate count of 46K. The maximum delay time for output to come after taking input for the proposed architecture is 18.514 ns and the currently operating frequency is 54 MHz.

Keywords

Deblocking filter, HEVC, FPGA, 4K UHD

First Page

4661

Last Page

4669

Recommended Citation

KHAN, AWAIS and RAJA, GULISTAN (2016) "FPGA implementation of a HEVC deblocking filter for fast processing of super high resolution applications," Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 24: No. 6, Article 9. https://doi.org/10.3906/elk-1407-144
Available at: https://journals.tubitak.gov.tr/elektrik/vol24/iss6/9