Design and implementation of a genetic algorithm IP core on an FPGA for path planning of mobile robots

Authors

ADEM TUNCER
MEHMET YILDIRIM

DOI

10.3906/elk-1502-122

Abstract

This paper presents a hardware realization of a genetic algorithm (GA) for the path planning problem of mobile robots on a field programmable gate array (FPGA). A customized GA intellectual property (IP) core was designed and implemented on an FPGA. A Xilinx xupv5-lx110t FPGA device was used as the hardware platform. The proposed GA IP core was applied to a Pioneer 3-DX mobile robot to confirm its path planning performance. For localization tasks, a camera mounted on the ceiling of the laboratory was utilized to receive images and allow the robot to determine its own location and the obstacles in the environment. In this way, procedures of path planning were tested in a real laboratory environment. An impressive time speedup was achieved when compared with its software implementation. Experimental results illustrate the effectiveness of the GA IP core hardware.

Keywords

Genetic algorithm, path planning, mobile robot, field programmable gate array, intellectual property core

First Page

5055

Last Page

5067

Recommended Citation

TUNCER, ADEM and YILDIRIM, MEHMET (2016) "Design and implementation of a genetic algorithm IP core on an FPGA for path planning of mobile robots," Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 24: No. 6, Article 37. https://doi.org/10.3906/elk-1502-122
Available at: https://journals.tubitak.gov.tr/elektrik/vol24/iss6/37