Low leakage power gating technique for subnanometer CMOS circuits

Authors

KAVITHA MANICKAM
GOVINDARAJ THANGAVEL

DOI

10.3906/elk-1410-175

Abstract

Static power has become the most important factor in the fabrication of integrated circuits. Power gating techniques minimize leakage currents and help to develop ultra-low-power and high-performance digital circuits. In this paper, a power gating approach is proposed to minimize leakage for subnanometer technologies. Simulation results reveal that the proposed technique reduces maximum of 96% leakage power, 33% dynamic power, 49% drowsy power, and 16{\%} energy as compared to conventional techniques. The proposed technique offers good leakage reduction, even under variation of different operating parameters.

Keywords

Leakage power, power gating, sleep mode, drowsy mode, charge recycling

First Page

5011

Last Page

5024

Recommended Citation

MANICKAM, KAVITHA and THANGAVEL, GOVINDARAJ (2016) "Low leakage power gating technique for subnanometer CMOS circuits," Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 24: No. 6, Article 34. https://doi.org/10.3906/elk-1410-175
Available at: https://journals.tubitak.gov.tr/elektrik/vol24/iss6/34