In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.
Digital arithmetic, redundant numbers, FPGA, FIR filters
ÇİNİ, UĞUR; AKTAN, MUSTAFA; and MORGÜL, AVNİ
"An alternative carry-save arithmetic for new generation field programmable gate arrays,"
Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 24:
2, Article 7.
Available at: https://journals.tubitak.gov.tr/elektrik/vol24/iss2/7