•  
  •  
 

Turkish Journal of Electrical Engineering and Computer Sciences

DOI

10.3906/elk-1212-43

Abstract

A linearization technique for improving the class-E power amplifier (PA)'s adjacent channel power ratio (ACPR) is proposed. The design is simulated in a 2-mu m InGaP/GaAs heterojunction bipolar transistor process. The integration of a passive predistorter at the input of the PA linearizes the proposed architecture. At a 29-dBm output power, the PA's ACPR is indicated to be -51 dBc, meeting the stringent code division multiple access regulation. At this exact output power, the simulated power added efficiency is 55 % with the collector voltage headroom consumption of 3.4 V. The input return loss, S11, of the PA is simulated as -12.5 dB. With an active finger print dimension of 1000 mu m \times 750 mu m, the proposed PA is well suited for the application of mobile wireless communication.

First Page

1210

Last Page

1218

Share

COinS