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Turkish Journal of Electrical Engineering and Computer Sciences

DOI

10.3906/elk-1206-18

Abstract

Vessel segmentation is important for many clinical applications, such as the diagnosis of vascular diseases, the planning of surgery, or the monitoring of the progress of disease. Although various approaches have been proposed to segment vessel structures from 3-dimensional medical images, to the best of our knowledge, there has been no known technique that uses magnetic resonance imaging (MRI) as prior information within the vessel segmentation of magnetic resonance angiography (MRA) or magnetic resonance venography (MRV) images. In this study, we propose a novel method that uses MRI images as an atlas, assuming that the patient has an MRI image in addition to MRA/MRV images. The proposed approach intends to increase vessel segmentation accuracy by using the available MRI image as prior information. We use a rigid mutual information registration of the MRA/MRV to the MRI, which provides subvoxel accurate multimodal image registration. On the other hand, vessel segmentation methods tend to mostly suffer from imaging artifacts, such as Rician noise, radio frequency (RF) inhomogeneity, or partial volume effects that are generated by imaging devices. Therefore, this proposed method aims to extract all of the vascular structures from MRA/MRI or MRV/MRI pairs at the same time, while minimizing the combined effects of noise and RF inhomogeneity. Our method is validated both quantitatively and visually using BrainWeb phantom images and clinical MRI, MRA, and MRV images. Comparison and observer studies are also realized using the BrainWeb database and clinical images. The computation time is markedly reduced by developing a parallel implementation using the Nvidia compute unified device architecture and OpenMP frameworks in order to allow the use of the method in clinical settings.

Keywords

Magnetic resonance imaging, magnetic resonance angiography, magnetic resonance venography, vessel segmentation, total variation, parallel processing, compute unified device architecture

First Page

499

Last Page

516

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