Early wakeup: improving the drowsy cache performance

Authors

SUNGHOON SHIM
SUNGWOO CHUNG
HONGJUN CHOI
CHEOL HONG KIM

DOI

10.3906/elk-1201-90

Abstract

As process technology scales down, leakage power consumption becomes comparable to dynamic power consumption. The drowsy cache technique is known as one of the most popular techniques for reducing the leakage power consumption in the data cache. However, the drowsy cache is reported to degrade the processor performance significantly. In this paper, to maintain the performance of the processor with the drowsy cache technique, we propose an early wakeup technique, which predicts the next cache line to be requested by utilizing the way-prediction information. The proposed technique efficiently reduces the number of accesses to the cache lines in drowsy mode. Our simulation results show that the proposed technique reduces the extra delay due to the drowsy cache scheme by 29.6%, on average.

Keywords

Processor architecture, low-power design, leakage power, drowsy cache, early wakeup

First Page

425

Last Page

433

Recommended Citation

SHIM, SUNGHOON; CHUNG, SUNGWOO; CHOI, HONGJUN; and KIM, CHEOL HONG (2014) "Early wakeup: improving the drowsy cache performance," Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 22: No. 2, Article 15. https://doi.org/10.3906/elk-1201-90
Available at: https://journals.tubitak.gov.tr/elektrik/vol22/iss2/15