A low-memory intensive decoding architecture for double-binary convolutional turbo code

Authors

MING ZHAN
LIANG ZHOU
JUN WU

Abstract

Memory accesses take a large part of the power consumption in the iterative decoding of double-binary convolutional turbo code (DB-CTC). To deal with this, a low-memory intensive decoding architecture is proposed for DB-CTC in this paper. The new scheme is based on an improved maximum a posteriori probability algorithm, where instead of storing all of the state metrics, only a part of these state metrics is stored in the state metrics cache (SMC), and the memory size of the SMC is thus reduced by 25%. Owing to a compare-select--recalculate processing (CSRP) module in the proposed decoding architecture, the unstored state metrics are recalculated by simple operations, while maintaining near optimal decoding performance.

DOI

10.3906/elk-1203-86

Keywords

Branch metrics, computational complexity, MAP algorithm, state metrics cache

First Page

202

Last Page

213

Recommended Citation

ZHAN, MING; ZHOU, LIANG; and WU, JUN (2014) "A low-memory intensive decoding architecture for double-binary convolutional turbo code," Turkish Journal of Electrical Engineering and Computer Sciences: Vol. 22: No. 1, Article 18. https://doi.org/10.3906/elk-1203-86
Available at: https://journals.tubitak.gov.tr/elektrik/vol22/iss1/18