Turkish Journal of Electrical Engineering and Computer Sciences




The discontinuous space vector pulse-width modulation (DSVPWM) is a well-known technique offering lower switching losses than continuous SVPWM. At the same, average switching frequency, or a switching frequency 1.5 times higher than utilized in continuous SVPWM, the discontinuous SVPWM results in lower current harmonic distortions than that obtained in continuous SVPWM at high modulation indices. This paper is concerned with the design and realization of new FPGA approach based a 5-segment discontinuous SVPWM operated at 40 kHz switching frequency. It will be shown that the implementation of the discontinuous SVPWM utilized in FPGA, to execute some complex tasks, is simplified through this new straightforward approach. For example, the judging of sectors, the computation of on-duration or firing pulses to control the switching of power switching devices can be executed much simpler with the proposed arithmetic logics or digital calculation in FPGA. In this way, the sampling frequency and hence switching frequency be increased. The SVPWM scheme has been implemented successfully based on APEX20KE Altera FPGA considering hardware resource saving. The validity of the proposed scheme has been tested experimentally to drive a 1.5 kW induction machine with low current harmonic distortions.


Discontinuous SVPWM, hardware resource saving, FPGA

First Page


Last Page