Field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor


Abstract: Elliptic curve cryptography provides a widely recognized secure environment for information exchange in resource-constrained embedded system applications, such as Internet-of-Things, wireless sensor networks, and radio frequency identification. As the elliptic-curve cryptography (ECC) arithmetic is computationally very complex, there is a need for dedicated hardware for efficient computation of the ECC algorithm in which scalar point multiplication is the performance bottleneck. In this work, we present an ECC accelerator that computes the scalar point multiplication for the NIST recommended elliptic curves over Galois binary fields by using a polynomial basis. We used the Montgomery algorithm with projective coordinates for the scalar point multiplication. We designed a hybrid finite field multiplier based on the standard Karatsuba and shift-and-add multiplication algorithms that achieve one finite field multiplication in $\frac{m}{2}$ clock cycles for a key-length of m. The proposed design has been modeled in Verilog hardware description language (HDL), functionally verified with simulations, and implemented for field-programmable gate array (FPGA) devices using vendor tools to demonstrate hardware efficiency. Finally, we have integrated the ECC accelerator as an AXI4 peripheral with a synthesizable microprocessor on an FPGA device to create an elliptic curve crypto-processor.

Keywords: Elliptic curve cryptography, Karatsuba multiplier, crypto-accelerator, crypto-processor, scalar multiplication, field-programmable gate array

Full Text: PDF